3D Memory Cells with High Performance Selectors: The Future!

Low temperature fabrication methodology for silicon selectors enables 3D RRAM stacking

Schematics of cross-bar array showing the (a) leakage current through cells not selected add to the current through the selected cell and (b) Two terminal bipolar selector devices are in series with memory to avoid leakage current.

Researchers have always been on a quest to cram more and more memory cells in a given area by reducing cell size. However, downsizing the state-of-the-art NAND flash technologies can result in performance issues. An alternative candidate proposed is a Resistive RAM (RRAM) which stores information in the form of resistance instead of charge. To make high density 3D RRAM stacks, low temperature processes (<450°C) that avoid melting of metal interconnects are required. Prof. Udayan Ganguly and his team have fabricated a low temperature selector diode required for RRAM crossbar array with improved OFF current, here at IIT Bombay.

An RRAM crossbar array comprises of oxide material sandwiched between pair of metal lines, called as word line and bit line. The resistance of oxide material can be changed by applying certain threshold voltages on these lines. To read the resistance, a small voltage is applied on a word line and the current is read through the bit line. However undesirable current paths can be triggered in this architecture. Hence, it is required to add additional elements called selectors in the array.

Selectors are diode like switches that block the path or allow conduction depending on the voltage applied.

Silicon based selector devices such as p-i-n diodes have shown excellent performance so far. But one bottleneck in the fabrication of these devices is the high temperature (700°C) growth process. This team came up with a p-i-n fabrication process at temperatures less than 430°C. Through experiments, the team also showed that the OFF current of these selectors can be decreased by reducing the impurities in the silicon. This fabrication methodology can enable 3D RRAM architecture with high performance silicon selectors.

- Reshma Krishnan

Published paper: R. Mandapati, S. Shrivastava, S. Vatsa, B. Saha, J. Schulze, U. Ganguly, “Improved Off-Current and Modeling in sub-430°C Si p-i-n Selector for Unipolar Resistive Random Access Memory” IEEE Electron Devices Letters, pp. 1310 - 1313, 2015.

Last updated on: 20-Jul-2022