For more than four decades, complementary metal oxide semiconductor (CMOS) transistors have enabled very large scale integration (VLSI) in integrated chips (ICs). This success is due to low standby power consumption by CMOS transistors, which allows shrinking and packing in millions of them in a single chip without worrying about power. In the past 15 years itself, the transistor channel length has scaled down from around 100 nanometres in 2000 to less than 15 nanometres today!
Scaling down further in this nanometre (‘nm’) regime brings us closer to atomic dimensions. Scientists now have to tackle new physical phenomena and quantum mechanical effects. These phenomena cause a various problems in device performance such as increased power consumption, high variability, lower reliability, etc. To counter these problems, novel CMOS transistor designs and fabrication techniques have been proposed by various researchers. Similar scaling problems are also present in memory chips and have resulted in the invention of novel memory devices.
Here are stories from our lab on some of advanced device designs and solutions being pursued.
Low temperature fabrication methodology for silicon selectors enables 3D RRAM stacking