This has been the traditional area of strength at IIT-Bombay since the early days of the Microelectronics group within the Electrical Engineering department. What began as a research program on MOS stacks, broadened significantly in scope & depth over the last decade, primarily due to the project on Centre of Excellence in Nanoelectronics (CEN), funded by the Ministry of Communication and Information Technology (MCIT), Govt. of India.
Our research on information processing devices now includes areas such as CMOS-based device reliability, technology-aware-design, advanced CMOS logic devices, advanced memory devices and beyond-CMOS approaches. This has led to hundreds of publications in high impact journals and conferences, tens of national & international patents, adoption of IITBNF techniques as industry standards, and millions of dollars in research funding from the global semiconductor industry. IITBNF is well-equipped with clean rooms and process tools for all essential device fabrication processes, and also houses state-of-the-art device simulation and characterization facilities. This includes commercial process tools (capable of handling 200 mm silicon wafers) donated by Applied Materials - the largest semiconductor equipment company in the world.
Some of our current research topics are:
|Non-classical CMOS logic devices – Source/drain engineering, gate-stack engineering, process integration for new materials, modeling & fabrication of Ge-based devices, FinFETs, nanowire FETs|
|Beyond-CMOS logic devices – modeling, fabrication and characterization of tunnel-FET for low-power applications, spintronic transistors and spin-valves for non-volatile logic applications|
|Magnetic semiconductors, complex oxides, 2D materials for novel logic and/or memory devices|
|Novel memory device technologies – modeling, fabrication and characterization of resistive RAM (RRAM) devices, spin-transfer-torque RAM devices|
|Biomimetic engineering & computation, memristive devices for neuromorphic computing|
|Semiconductor device reliability studies – bias-temperature-instability and hot carrier degradation in high-k/metal-gate stacks|
|Bottom-up approaches to CMOS scaling|
Saurabh Lodha, Udayan Ganguly, Bipin Rajendran, Dipankar Saha, Swaroop Ganguly, Ashwin Tulapurkar, Anil Kottantharayil, Souvik Mahapatra, M. Shojaei Baghini, V. Ramgopal Rao, Dinesh Sharma, J. Vasi
3D Memory Cells with High Performance Selectors: The Future!
Low temperature fabrication methodology for silicon selectors enables 3D RRAM stacking
Contacting transistors of the future
Experimental proof of the n-type nature of Au and Pd contacts to MoS2, a promising material for making 2D transistors
Tuning the Material for Good Memory
Identifying the right composition and thickness of hafnium oxide films for RRAM devices
Speedy Prediction of a Chip’s Lifetime
A robust compact model predicts and compares the lifetime of transistors fabricated using different processes
Tweaking the Transistor below 10 nm
Novel structural modifications predict robust functioning at these extreme length scales
Nanoscale Device Mimics Neuron Junctions in the Brain
Tunable resistance of an oxide thin film can be used to imitate the working of a synapse