Contacting Transistors of the Future

Experimental proof of the n-type nature of Au and Pd contacts to MoS2, a promising material for making 2D transistors

Schematic diagram of a test transistor structure used to study electrical contacts between MoS2 and metals

Most smartphones today are faster than the supercomputer that NASA used to send astronuts to the moon in 1969. This amazing improvement in performane and affordability of computers in last few decades is due to downscaling the size of transistors - the basic building block of computers. To continue this evolution, few years from now, transistors will have to be made using utterly thin materials rather than bulk materials used today, to have better electrostatic control over its operation. Prof. Lodha’s team at IITBNF has made notable contribution to the development of these transistors.

Transistors are tiny switches that can be turned ‘on’ or ‘off’ by electrical signals. They have three terminals: source, drain and gate. The current between source and drain is controlled by the voltage applied at the gate. As transistors get smaller, the source and drain terminals get so closely coupled that it becomes extremely difficult to control the current between them through the gate. In such situations, 2D materials like graphene and molybdenum disulphide (MoS2) can provide an excellent channel for current conduction between the source and drain, while maintaining gate control.

To make practical devices using these unusual materials, the nature of their contact with metals needs to be closely understood. When a metal’s free energy levels are aligned close to the conduction band of the channel material, it aids the flow of electrons (i.e. an ‘n-type’ contact). When aligned close to the valance band (i.e. in a ‘p-type’ contact), it favours the flow of holes.

Theoretically, gold (Au) and palladium (Pd) are expected to form p-type contacts to MoS2. However, detailed experiments by Mr. Kaushik and others from Prof. Lodha’s group, in collaboration with Prof. Deshmukh’s team at Tata Institute of Fundamental Research (TIFR), Mumbai, have determined them to be n-type using photocurrent mapping. This is a crucial result for the development of ultra-thin CMOS transistors in the future.

- Sanchar Acharya

Work funded/ supported by: Department of Science and Technology (DST), Government of India.

Published paper: Naveen Kaushik, AnkurNipane, Firdous Basheer, Sudipta Dubey, Sameer Grover, Mandar M. Deshmukh and Saurabh Lodha, “Schottkey barrier heights for Au and Pd contacts to MoS2 Applied Physics Letters, Vol. 105, pp. 113505(2014).

Last updated on: 20-Jul-2022