A robust compact model predicts and compares the lifetime of transistors fabricated using different processes
Be it in a phone or a spacecraft; while a computer chip can be used in every aspect of modern life, it is just as important for us to predict its lifetime. It turns out that chips with unknown lifetimes can cause serious performance failures. Typically, a chip lasts for a few years. But existing methods to predict its lifetime take as long as a few months! Prof. S. Mahapatra’s team in IITBNF has developed a mathematical model that can quickly predict the lifetime of a transistor, i.e. the basic building block of any chip, depending on the way it has been fabricated.
Computer chips today consist of more than a billion transistors, known as MOSFETs. Approximately half of them are p-channel devices (pMOSFET) that require negative voltages to operate. Continuous device usage typically leads to rising temperatures in a chip. And when pMOSFETs are operated using negative voltage at elevated temperatures, their turn-on voltage and operating current degrade with time. This degradation effect in pMOSFETs is known as negative bias temperature instability (NBTI). The compact model developed by Prof. Mahapatra’s team predicts and compares the impact of NBTI on pMOSFETs when fabricated using different process-technologies.
NBTI arises due to creation of defects, called as traps, in the gate oxide and at the channel-oxide interface of a MOSFET. The team’s model includes contributions from these traps. It also includes a few fabrication process based parameters that can be easily determined by short-time (2-3 hours) experimental measurements. The lifetime predictions of this model are found to be as accurate as long-time experimental tests. This accurate mathematical model that includes process dependent variations in a very simple manner can speed up the calculations of a chip’s lifetime.
Work funded/supported by: Applied Materials, Inc. & Department of Electronics & Information Technology (DietY), Government of India.
Published paper: Kaustubh Joshi Subhadeep Mukhopadhyay, Nilesh Goel, Nirmal Nanaware, Souvik Mahapatra, “A Detailed Study of Gate Insulator Process Dependence of NBTI Using a Compact Model” IEEE Transactions on Electron Devices, Vol. 61, No. 2, pp. 408 (2014).