Structural modifications to existing architectures predict lower programming currents in Phase Change Memory cells
A neatly arranged stack of books and a shabby book shelf - even if they both house the same books, they are easily distinguishable. Phase Change Memory (PCM) – a novel memory architecture, uses this particular feature of random or ordered atomic arrangement in certain materials for to distinguish between a digital ‘0’ and ‘1’. Prof. B. Muralidharan and his team have predicted a new structure for this kind of a memory which requires lesser current to make a transition between 1 and 0 and vice-versa.
PCM makes use of the phase change behaviour of chalcogenide materials. These materials can switch between two stable physical states by applying a current, also known as programming current. The two states are the crystalline state which has a long range order for the arrangement of atoms in it and the amorphous state which has no order at all in the material. Since crystalline state has long range order it offers less resistance whereas the amorphous state offers higher resistance to the programming currents. This determines whether a ‘0’ or a ‘1’ is stored in the cell.
This group at IIT Bombay has proposed a new architecture for the vertical nanopillar PCM cell. They have incorporated a new SiGe layer near the bottom electrode which shifts the active transition region towards this bottom electrode (the red region in figure).This placement of the active region reduces the heat lost during programming and also increases the temperature of this transition region. The combined effect is that the programming currents are reduced. They have also introduced a taper in the architecture which improves the heating in the active region. The simulated structure shows a 60% reduction in programming currents which is very promising for PCM since moderate or high programming currents are one of the major drawbacks of this technology.
- Reshma Krishnan
Work funded/ supported by: IIT Bombay SEED grant and Center of Automotive Energy and Materials, ARCI, IIT Madras Research Park.
Published paper: J. Bahl, B. Rajendran and B. Muralidharan, “Programming Current Reduction via Enhanced Asymmetry-Induced Thermoelectric Effects in Vertical Nanopillar Phase-Change Memory Cells”, IEEE Trans. Elec. Dev, 62, 12, 4015-4021, (2015).