Tweaking the Transistor below 10 nm

Novel structural modifications predict robust functioning at these extreme length scales

Primary structural difference between a conventional FinFET and a new design proposed by the IITBNF team – the EDFinFET

Over decades, engineers have built powerful computer chips by shrinking the unit transistor size inside it. Today, processors in most new laptops contain transistors that are smaller than 25 nm. These transistors are FinFETs (Fin Field Effect Transistors) – unique devices that work better than conventional transistors at the nanometre scale. However, on making them smaller than 15 nm, FinFETs are seen to be unstable in their performance. Prof. U. Ganguly’s team at IITBNF have designed a solution - the EDFinFET.

EDFinFET builds on the structure of the original FinFET, which is a transistor that has a fin-shaped channel surrounded by the gate terminal. Complex manufacturing processes are required to fabricate these FinFET structures. Small deviations that generally occur in a fabrication process cause variations in fin size and shape. This drastically alters the transistor turn-on voltage and currents, especially at dimensions of 15 nm & below. The new transistor designed at IITBNF has been computed to be more resilient to process variations at length scales of 15 nm and 10 nm. This has been achieved by adding an epitaxial layer of constant thickness over the fin – hence the name, Epitaxially Defined FinFET or EDFinFET.

In EDFinFET, the epitaxial layer forms the channel. Since it is added after the fin is made, its thickness is independent of fin variations. Hence, the transistor turn-on voltage and currents are more stable. Additionally, the team has calculated EDFinFET’s performance in a dynamic threshold (DT) arrangement – where the same voltage is simultaneously applied to both transistor gate and body terminals. This configuration further improves the robustness of a 10 nm device and also boosts current values by 43%. These results show EDFinFET to be a promising new transistor design to tackle practical challenges at extreme length scales.

- Rajashree Nori

Work funded/supported by: Dept. of Science & Technology (DST) of Government of India (GoI); Applied Materials Inc.

Published paper: Sushant Mittal, Shashank Gupta, Aneesh Nainani, Mathew C. Abraham, Klaus Schuegraf, Saurabh Lodha and U. Ganguly, “Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology” IEEE Transactions on Electron Devices, Vol. 61, No. 8, pp. 2711 (2014).

Last updated on: 20-Jul-2022