Talk: Role of Advanced Film Deposition Technology to Enable the Future of Patterning

Dear All,
Department of Electrical Engineering, IIT Bombay in association with The Centre for Semiconductor Technologies (SemiX), IIT Bombay is organizing a talk by Sudipto Naskar, Principal Engineer and Program Manager in Thin Films Technologies at Intel Corporation. All are cordially invited for the talk. The details of the talk are as follows:

• VENUE: GG301, Seminar Room, 3rd Floor, GG Building, EE Department, IIT Bombay
• TIME: Tuesday, 7th January 2025 at 2:00 PM to 3:30 PM
• TITLE: Role of Advanced Film Deposition Technology to Enable the Future of Patterning

As we enter the Angstrom era of transistor scaling, the challenges associated with patterning smaller features using conventional lithography are becoming increasingly complex. Even with the adoption of EUV lithography, critical dimensions for future technology nodes present significant variability challenges for high-volume manufacturing.

Key Highlights of the Talk:

• Integrated Lithography Techniques: Explore SADP and SAQP methods that utilize precise thickness control and high conformality in film deposition processes.
• Transition from CVD to ALD: Understand the shift from Chemical Vapor Deposition (CVD) processes for feature sizes greater than 100nm to Atomic Layer Deposition (ALD) processes necessary for smaller dimensions.
• Bottom-Up Alignment Techniques: Discover novel techniques aimed at improving pattern placement accuracy and addressing edge placement challenges.
• Selective Dielectric Deposition: Discuss critical aspects of selective dielectric deposition, including defect identification and mitigation strategies.

Abstract:

With transistor scaling entering Angstrom era, the ability to pattern small features using conventional lithography is becoming ever challenging. Even with the adoption of EUV lithography technology the critical dimensions of future tech-nodes pose severe variability challenges for high volume manufacturing. Thus, to achieve aggressive scaling, integrated lithography techniques like SADP and SAQP are being employed that takes advantage of precise thickness control and high conformality of film deposition processes. CVD processes have long played its role for feature sizes >100nm. To print CD sizes lower than that, ALD processes are necessary. Further, to enable precise alignment of photomasks, there is a need to develop novel techniques that enables bottom-up alignment to improve pattern placement accuracy. Area-selective deposition is one such way to promote self-alignment to address edge placement challenges. While such processes look attractive from self-alignment standpoint, there are several challenges to make these processes high volume worthy. Surface preparation, length of passivation and defect mitigation are to name a few. In this presentation, these critical aspects of deposition processes will be covered with particular emphasis on selective dielectric deposition. The importance of defect identification and mitigation techniques will be discussed in the realm of various applications.

About the Speaker:

Sudipto Naskar is a recognized leader and innovator in the semiconductor industry, with over 15 years of experience in thin films and diffusion. He has successfully led cross-functional teams to develop high-volume manufacturing process modules. He has played a pivotal role in process innovations for 7nm technology nodes. The talk promises to provide valuable insights into the future of semiconductor technology, and we encourage all students, faculty, and staff members to attend. We look forward to seeing you there! For more information, please contact: SemiX Office (office.semix@iitb.ac.in)